Ruslan Hasanov
ENDE
All work

case study

Team of 3

LLM-agent hardware verification flow

An LLM agent that writes SystemVerilog testbenches, checked by three other agents

Period
04/2026 – 08/2026
Context
TU Ilmenau, team of 3. I contributed to all parts of the agent: design, implementation and evaluation.

Problem

Hardware verification needs SystemVerilog testbenches. We built an LLM agent to write them, and a way to check its output without trusting a single model.

Approach

  • Python agent with LangGraph and tool use writes the testbenches.
  • Three checker sub-agents review the output and decide by majority vote.
  • Evaluation on VerilogEval designs with mutation testing.
  • Team of 3. My part: design, implementation, evaluation.

Results

  • A working agent that writes SystemVerilog testbenches.
  • 3 checkers, majority vote, evaluated on VerilogEval with mutation testing.

Worth noting

Three checkers vote instead of trusting one model, and mutation testing scores the result.